1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to circuit elements, such as field effect transistors, and manufacturing techniques based on strain-inducing mechanisms using stressed material layers.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements located on a given chip area according to a specified circuit layout, wherein, in complex circuits, the field effect transistor represents one predominant circuit element. Generally, a plurality of process technologies for advanced semiconductor devices are currently practiced, wherein, for complex circuitry based on field effect transistors, such as microprocessors, storage chips, graphic devices and the like, MOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using MOS technology, millions of transistors, i.e., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially determines the performance of MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, may be a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One issue associated with reduced gate lengths is the occurrence of so-called short channel effects, which may result in a reduced controllability of the channel conductivity. Short channel effects may be countered by certain design techniques, some of which, however, may be accompanied by a reduction of the channel conductivity, thereby partially offsetting the advantages obtained by the reduction of critical dimensions.
In view of this situation, it has been proposed to enhance device performance of the transistor elements not only by reducing the transistor dimensions but also by increasing the charge carrier mobility in the channel region for a given channel length, thereby increasing the drive current capability and thus transistor performance. In this manner, performance of sophisticated logic circuitry may be enhanced, for instance, in a microprocessor, the performance per watt of consumed power may be increased. In promising approaches, the lattice structure in the channel region may be modified, for instance, by creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region of a silicon layer having a standard crystallographic configuration may increase the mobility of electrons, which in turn may directly translate into a corresponding increase of the conductivity of N-type transistors. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
One efficient approach in this respect is a technique that enables the creation of desired stress conditions within the channel region of transistor elements by adjusting the stress characteristics of a dielectric layer stack that is formed above the basic transistor structure when the contact level of the device is formed. The contact level, comprised of an interlayer dielectric material and contact elements, may be understood as an interface between the individual semiconductor circuit elements and a complex wiring system or metallization system in which metal lines and vias may provide the complex network of electrical connections. The dielectric layer stack of the contact level typically comprises one or more dielectric layers which may be located close to the transistor and which may also be used in controlling a respective etch process in order to form contact openings connecting to the gate and drain and source terminals. Therefore, an effective control of mechanical stress in the channel regions, i.e., an effective stress engineering, may be accomplished by adjusting the internal stress of one or more of these layers, which may also be referred to as contact etch stop layers, and by positioning a contact etch stop layer having an internal compressive stress above a P-channel transistor and/or by positioning a contact etch stop layer having an internal tensile strain above an N-channel transistor, thereby creating compressive and tensile strain, respectively, in the respective channel regions.
Typically, the contact etch stop layer is formed by plasma enhanced chemical vapor deposition (PECVD) processes above the transistor, i.e., above the gate structure and the drain and source regions, wherein, for instance, silicon nitride may be efficiently used due to its high etch selectivity with respect to silicon dioxide, which is a well-established interlayer dielectric material. Furthermore, PECVD silicon nitride may be deposited with a high intrinsic stress, for example, up to 3.6 Giga Pascal (GPa) of compressive stress and up to 1.6 GPa of tensile stress, wherein the type and the magnitude of the intrinsic stress may be efficiently adjusted by selecting appropriate deposition parameters in order to provide a certain amount of hydrogen in the silicon nitride material, thereby obtaining, in combination with a specific molecular structure, the desired type of stress. For example, ion bombardment, deposition pressure, substrate temperature, gas flow rates and the like represent respective parameters that may be controlled for obtaining the desired intrinsic stress.
The resulting strain level in the channel regions of the adjacent transistor elements is determined by the internal stress level of the dielectric materials, the amount of the stressed dielectric material and the effective offset of the stressed material from the channel region. Consequently, for a given device geometry, the strain level in the channel region is typically increased by increasing the internal stress level of the dielectric materials and also increasing the layer thickness of the dielectric materials. During the ongoing scaling of sophisticated semiconductor devices, however, the layer thickness of the stressed dielectric material is limited by the deposition capabilities of the PECVD techniques and the resulting sophisticated surface topography caused by the gate electrode structures of the transistor elements, in particular when densely packed device regions are considered. Furthermore, in some conventional approaches, a so-called “dual stress liner” approach may be applied in which a compressively stressed dielectric material is positioned above the P-channel transistor while a tensile stressed dielectric material is formed above the N-channel transistor, thereby requiring sophisticated masking and patterning regimes, which may also require a reduced layer thickness in order to avoid deposition and patterning related irregularities, such as voids, undue material residues and the like.
Upon further device scaling, in particular in sophisticated semiconductor devices, a distance between neighboring gate electrode structures may reach values of approximately 40 nm and even less, which may thus require a further reduction of the thickness of the contact etch stop layers, in particular when deposition-related irregularities are to be avoided. Consequently, for given deposition recipes for silicon nitride materials, which may result in intrinsic stress levels of the above-specified magnitudes for tensilely and compressively stressed materials, the overall efficiency of dual stress liner approaches may significantly decrease, thereby making these approaches less attractive, in particular when taking into consideration the significant degree of process complexity involved in the deposition and patterning of the differently stressed etch stop materials. For this reason, an efficient strain-inducing mechanism may be preserved for one type of transistor, for instance for P-channel transistors requiring a high compressive stress level in the silicon nitride material, whereas the internal stress level of the silicon nitride material positioned above N-channel transistors may be efficiently “relaxed” by performing a masked ion implantation process on the basis of appropriate implantation species, such as xenon, germanium and the like. During the ion bombardment, the heavy xenon or germanium species creates heavy damage in the molecular structure of the compressively stressed silicon nitride material, for instance, by destroying corresponding bonds within the dielectric material. On the other hand, the heavy ion bombardment may also give rise to additional irregularities, such as particle contamination by sputtering off material from exposed material surface areas, and the like. Moreover, due to the nature of the ion bombardment, the implantation parameters, such as energy and dose, have to be correctly selected in order to essentially confine the implantation species to the dielectric material under consideration, which may, however, be extremely difficult due to the pronounced surface topography and the variability of penetration depth during an implantation process. As an example, a reduced implantation energy may result in a less efficient stress relaxation, while an increased implantation energy may cause a reduction in transistor performance, for instance, by incorporating a significant amount of implantation species in other device areas, by modifying the surface structure of material layers, such as semiconductor regions, metal silicide regions and the like.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.